pg=1( segmenation and paging continued……) – Part 2

Continution from previous post on the same topic.. If you haven’t read , please read it here..

 

Now, let us discuss about paging: The paging unit action can be fetched in detail from vendor documents , once again RTFM.

If you know  there are control registers 🙂  those plays an important role in paging process..

CRs to think abt :
———————–

CR{0,2,3,4}

CR3 -> PGD /PDPTE/ PML4
^^^^ This is an important register which points to any of the above accordingly..

CR0 -> PAE

^^^^ Physical Address Extension flag in this register make the ‘pae’ feature to be enabled . .. In effect, in this mode it can support 64 G of RAM..

CR4 -> PSE

^^^^ Page Size Flag helps to go for big size pages than normal page size like 4KB.

CR2 -> Page Fault Exception code

^^^ When the process tries to access the memory area which does not belongs to them or a process running in user mode try to access memory with less previlege mode, there will be a page fault exception generated.. The page fault exception details will be stored in “cr2”..

Now, I would like to discuss about the different paging modes described in x86 arch…

There are mainly 3 paging modes..

*** I am not good at drawing, so the simple ascii art ****

1) 32 bit paging:

————————————-
|  10   bits   | 10   bits| 12 bits |
————————————-

Page Dir     PTE          offset

2) PAE mode:

____________________________________
|2 bits | 9 bits | 9 bits | 12 bits  |
|____________________________________|

PDPTP  PD       PT         offset

3) IA32e mode ( In intel terms )

____________________________________________
|9 bits | 9 bits | 9 bits | 9 bits |12 bits  |
|_______|________|________|________|_________|

Now, let me go back and describe about ‘page tables and pages’ .. To emulate a feeling that, all the processes running in linux ‘own’, all of  the ‘physical memory’ the concept called “virtual address space” has introduced.. All the processes got its own virtual address space.. The virtual address space is contiguous, but it is logical.. The virtual addresses are pointing to physical addresses, in linux terms “page frames”. The page frames/pages got its own protection flags which control access rights.. It is not necessary that the pointed page frame is present in physical ram when it derived.. It will end up in ‘page fault’ which can bring the page back to memory (aka demand paging). What else ? hmmmm..yeah, also, the pages can be saved in disk and written back (aka swapping in/out) to memory .. thus achieving 2 page frames with the same data..

The number 1# OS ( Linux ) adopted a common mechanism for addressing above three modes of paging.. The story was bit different before “2.6.10” version as shown below.

<= 2.6.10 –> 3 level paging for 64 bit

> 2.6.10  –> 4 level paging for 64 bit

That said, linux keep below chain of paging directories for converting a ‘virtual address’ to ‘physical address’

PGD -> PUD -> PMD -> PT -> page

32 bit mode ( with PAE =0) PUD and PML are “0” bits , thus 2 level paging
32 bit mode ( with PAE=1 ) PDPT == PGD, PUD (eliminated) , PD==PML, PT=PT , thus 3 level paging
64 bit mode  ( with PAE =1 ) PGD, PUD, PMD, PT => page

Do you allow me to stop here ? 🙂

Feel free to ask your questions as comments, I will be glad to answer that..

ps# bit lazy to dump() all bits  and  my fingers put a pause() here.. 🙂 Cya in next article..

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